Daniel@chezpaley.com (650) 868 - 9014


20+ years in hardware/ASIC/IP architecture, design, implementation and verification experience. International project and team management experience. Expert in RFID standards, architectures and implementations. Proven ability to perform and excel in diverse cultural environments as a participant and a hands on leader.

Proven Verilog design and verification experience (RTL through database design)
Technical and Program management (including international program management)
Embedded Programming experience (assembly, C/C++)
Architecture, Design, and Implementation of Industry Standards (RFID, 1394, MPEG, etc)


Director of Software Engineering, Applied Wireless ID Group (AWID) 2005 – Present

Developed and architected company’s first product line of Software defined RFID Readers. Responsible for all aspects of the Tahoe program. Implementation of FPGA design, embedded software, and algorithm design.
Worked with EPC Global (standards organization) to develop software standards. Co-Chair Application Level Events Working Group; Lead the CTE sub-committee of the Reader Operations Working group. Presented and lead technical discussions at both the general SAG meetings and Reader Operations meetings
Instrumental in the process of reaching consensus in setting the C1G2 specification. Worked with fellow members of the standards committee and staff of EPC Global.
Developed and maintained working relationship with partners and suppliers to keep development on schedule. Resolved problems with a positive outcome for all parties.

Director of Systems and Protocols, Intelleflex Corporation 2004 – 2005

Developed and architected company’s first product line of Class-3 RFID tags and systems. Authored several architecture specifications for the product line. Responsible for all embedded tag software (architecture, implementation, design and debug).
Worked with EPC Global to develop the Class-1 Generation-2 UHF RFID standard. Co-chair of Hardware Action Group Technical sub-committee. Presented at the general HAG meeting the findings of the sub-committee.
Instrumental in the process of reaching consensus in setting the C1G2 specification. Worked with fellow members of the standards committee and staff of EPC Global.
Developed and maintained working relationship with key partners and suppliers. Responsible for development schedule. Debugged key system related issues with a positive outcome.

Contractor, Virtual-Silicon. 2003

Developed, architected, implemented and verified three technology important test chips, completing the contract requirements on time using Verilog and Perl.

Sr. ASIC Designer, Xerox Corporation, Impact Group 1999 – 2002

Successfully completed the architecture and design of the interconnect unit for the Image Processor project. This allowed up to 64 processors to be connected for increased processing power, allowing commands and data to be routed in the most optimal path possible.
Architectural design and implemented microcode of color conversion module in development of the MXP5800 Digital Media Processor chip. This processor was created in partnership with Intel.
Initiated and lead the evaluation, research, and development of methodology tools responsible for improved internal and external communications. Devised a set of methodologies and tools, which allowed for creation and maintenance of products.
Created, implemented and maintained a web and email based Bug/Issue tracking software package to follow onsite and offsite issues associated with all architecture, design and implementation for the department.
Developed standardized directory structure incorporating design repositories, testing, and code development for both hardware and software, which facilitated design reuse.

Principal Engineer, Manager, Project Lead, Phoenix Technologies Ltd., 1998 –1999 Virtual Chips Division

Managed, led, architected, and designed the Multimedia Link core for 1394a (with MPEG and 61883 enhancements) project resulting in customer on time shipment of their product.
Managed international engineering team. Provided leadership and training for all aspects of Test Environment product.
Architected, designed, and developed Test Environment for 1394a project, which received a U.S. patent.
Architected, designed, and developed Accelerated Graphics Port (AGP) Host Controller core. Managed design team to complete Host core using Verilog. Continued ongoing support with Applications, Sales, and Marketing.

Project Leader, Design and Verification, Vadem 1995 – 1996

Managed the successful completion of the VG330, an SOC microcontroller. Significantly improved existing verification for design and test for manufacturing

Member of Technical Staff, Rambus Inc 1991 – 1995

Initiated and led design verification of first-generation RDRAM product resulting in successful product launches and continued company success.
Verified and debugged RAC and RDRAM second-generation products for LSI and Nintendo projects in a condensed schedule time frame.
Initiated and designed video and computer interfaces of demonstration project that showcased the high-speed memory design.

Design Engineer, Olivetti Networks and System 1989 – 1991

Developed EISA design for I860 workstation in partnership with Microsoft. Implemented protocol design in a non-x86 architecture system.
Architected, and developed service processor board for minicomputer system, which allowed for real time data collection and system maintenance.
Implemented PLL Clock Chip for minicomputer system, which required less than 2ns of clock skew between all chips in the system. Completed this development from debug through tape out, and test vector generation.

Design Engineer, CAE Link Flight Simulator Corporation. 1986 – 1989 (Formerly Singer Link Flight)

Designed LANTIRN simulator project board one, which simulated different graphic views with symbology and text overlays.
Completed Priority Sectoring Processor of the Digital Image Generator. Implemented bug fixes in documentation and hardware both at onsite and offsite locations, which was critical in customer acceptance tests.


Bachelor of Science, Computer Engineering (1986) University of the Pacific, Stockton, California


Patent Number: 6,457,152, Device and Method for testing a device through resolution of data into atomic operations. Granted Sept 24, 2002.

Eight additional patents filed in the area of RFID.